Intel fixes for Plundervolt; SiFive automotive core;
Internet of Things
Western Digital Corp. and Codasip are working together on Western Digital’s SweRV Core EH1, which is a RISC-V core with a 32-bit, dual superscalar, 9-stage pipeline architecture. The core, launched earlier this is aimed at embedded devices supporting data-intensive edge applications, such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems. Codasip is offering support package for SweRV, which includes components, tools and technical support.
Dialog Semiconductor has a strategic agreement with Flex Logix to license Flex Logix’s EFLX Embedded Field-Programmable Gate Array (eFPGA) technology for use in high volume semiconductor ICs. Dialog will also use EFLX Compiler to program these embedded FPGAs. EFLX is not a standalone chip but a low-power FPGA that is can be inserted into SoCs, microcontrollers and other ICs.
RISC-V is making its way into automotive and AI. SiFive announced new processor cores for Apex for mission-critical processors and SiFive Intelligence for deep learning markets. SiFIVE Apex has open-source Kami for parametric verification and parameterized cores that customers can configure. The company Resiltech is working with SiFive to achieve ISO 26262. The Intelligence processor cores can be used in configurable designs for audio, speech or vision processing, to inference processing and machine learning.
Using Synopsys’ DesignWare ARC Processor IP, Calterah Semiconductor’s Automotive Radar SoC — a millimeter wave CMOS radar SoC — is now in mass production. The chip series, called Alps, has no more than four transmitter channels, four receiver channels, a waveform generator, an ADC with sampling rates up to 50 million of samples per second, according to a press release. Calterah used an ISO 26262-compliant process and Synopsys’ ASIL-compliant ARC EM6 Processor and ARC MetaWare Development Toolkit for Safety in the hardware and software development of its safety-critical automotive SoC.
Intel issued fixes this week for its ‘Plundervolt’ Software Guard Extensions (SGX) flaw, which researchers from separate universities found earlier this year. The flaw in voltage feature of SGX, a security firmware that Intel added to processors used in computer laptops, desktops and servers makes it possible for attackers to change the voltage levels in chips in a way that reveals AES encryption keys. As Intel describes it, “Improper conditions check in voltage settings for some Intel Processors may allow an authenticated user to potentially enable escalation of privilege and/or information disclosure via local access.” Intel recommends that users of the processors in its 6th, 7th, 8th, 9th & 10th generation core processors, Xeon processor E3 v5 & v6, and Xeon processor E-2100 & E-2200 families should update to the latest BIOS version provided by the system manufacturer that addresses these issues. An SGX TCB key recovery is planned for later in Q1 2020. University of Virginia Professor Irfan Ahmed, who runs the Security and Forensics Engineering (SAFE) Lab, goes farther. “Businesses should begin immediately diversifying and randomizing their CPUs,” he writes in a Dark Reading blog, in reference to six other flaws in Intel’s chips.
Rambus has completed acquisition of the silicon IP, secure protocols and provisioning business from Verimatrix for $45 million plus up to an additional $20 million depending on revenue levels. “The addition of this business from Verimatrix augments our portfolio of mission-critical embedded security products and expands our offerings for data center, AI, networking and automotive,” said Luc Seraphin, president and CEO of Rambus, in press release.
Enflame Technology will be using Rambus’s HBM2 Memory Subsystem solution for it’s AI training chip.
Global Unichip is using Cadence’s Digital Implementation and signoff flow for its advanced-node designs for AI and HPC applications. Cadence’s Innovus Implementation System and Voltus IC Power Integrity Solution enable GUC to achieve first-pass silicon success and meet GHz performance target for multi-billion gate designs